Semiconductor circuit manufacturing is subject to certain design rules for laying out features on wafers. As semiconductor circuits become more highly integrated, it is important to design semiconductor chips in such a manner as to provide more elements on a chip for a higher yield in the final product. The minimum feature size depends on the chemical and optical limits of a particular lithographic system, and the tolerance for distortions of the shape. Variation of a critical dimension can be caused by line edge roughness (LER) occurring during lithographic processing of the semiconductor wafer. For contacts or other closed contours on an integrated circuit, their shapes and orientations, including LER, are of significant concern for generating design rules and assessing process capability for the manufacturing of integrated circuits.
Conventionally, a single ellipse is used to fit closed contours, such as contacts, to determine their shape. Then, LER is characterized by fitting the shape and calculating the standard deviation of the residuals. The frequency components of the roughness can thus be retrieved. For contacts or any other closed contours on the chip, usually the shape information which contains both orientation and low frequency components of the edge is the key factor for the function of the device. However, the traditional methods do not provide shape information, and the detailed roughness information at specific orientations is lost and cannot be retrieved.
A need therefore exists for an improved method for accurately determining both the shape and orientation of closed contours on a semiconductor chip, especially at the 22 nanometer (nm) and 15 nm technology nodes.